BY THE early 1900s, Manhattan residents were finding life on the ground a
little crowded. Their solution was simple: as land prices soared, so did the
buildings. A century later, computer chip manufacturers are facing a similar
crisis. They need to pack more and more components onto their chips, so silicon
real estate is at a premium. The strategy so far has been to make each
transistor ever smaller, but the limits of miniaturisation are fast approaching.
So how are engineers to make the more powerful and faster chips that the
computing industry constantly demands?
The obvious answer is to follow Manhattan鈥檚 example and build silicon
skyscrapers. Teams of computer architects are drawing up plans for this new
cityscape, and one ambitious group is working on a strange idea that involves a
fluid sea of connections. If they鈥檙e as successful as New York鈥檚 developers,
computers could get hundreds of times faster.
For a long time, advances in chip technology have put off the need for this
jump into the third dimension. Back in 1965, Gordon Moore, co-founder of chip
maker Intel, enshrined the relentless trend towards miniaturisation in a law:
the number of processors packed into a given area doubles every eighteen
months.
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But last year, David Muller and colleagues from Bell Laboratories鈥� research
arm, Lucent Technologies, predicted that Moore鈥檚 law will break down at the
beginning of the next decade (Nature, vol 399, p 758). The barrier to
indefinite miniaturisation is the size of the silicon layers in each transistor.
Muller鈥檚 team say that no device fewer than four atoms thick could work.
If present trends continue, this limit will be reached by 2012. Even Moore is
expressing doubts: 鈥淲e really are running up against the problems of materials
not behaving in small pieces the way they do in bigger chunks. The physics
starts changing.鈥� Alternatives to silicon technology鈥攎olecular or quantum
computers for example鈥攇enerate plenty of publicity, but no one is sure if
they鈥檒l ever be found in desktop machines.
To people outside the industry, the problem seems strange. Chips are tiny
things鈥攜ou can fit several inside a matchbox. If it鈥檚 so vital to cram in
more electronics, why not just make a bigger chip? Computer chips start life as
part of a wafer of silicon about the size of a dinner plate onto which the
components of around 150 chips are etched. The wafer is never a perfect surface,
so some of these chips are bound to be faulty. Few factories exceed a 50 per
cent success rate, and the larger the area of silicon that a chip requires, the
more likely it is to contain a fault. Bigger chips could certainly accommodate
more processors, but there鈥檚 no point making them if they don鈥檛 actually
work.
If expanding sideways is out, the only way is up: stacking ordinary chips on
top of each other to create a 3D version. Each chip can be checked before it鈥檚
stacked, ensuring reliability isn鈥檛 compromised. But for the engineers working
on the problem, it has been a frustrating challenge. Stacking layers of silicon
and insulating each layer is tricky enough, but what鈥檚 actually needed is even
tougher. The chip layers must be connected鈥攁nd making and controlling
these connections has defeated the industry until now.
Over the edge
One answer is to send the connections round the edge of each wafer. Irvine
Sensors of Costa Mesa, California, has made edge-connected systems that the US
Army plans to use in wearable computers. The company claims to have produced
鈥渃omputers-on-a-stack鈥濃��52-layer sandwiches made up of 10 different types
of chip. They pack processor, interface and memories into cubes not much bigger
than ordinary dice. Although this system is powerful, wiring the layers together
is laborious, so this is an expensive solution, probably only affordable by the
military.
But why go round the edge? If the two chips are sitting on top of each other,
wouldn鈥檛 it be easier to go straight through the silicon layers, sending wires
vertically between them like girders in a multi-storey building? Vertical
routing is not a new idea. It is rumoured that the US government and
manufacturers such as Intel have invested around $60 million in this
technology, but they are still waiting for their pay-off. Inserting wires
through a silicon wafer, and insulating these connections, has so far defeated
the industry.
In California鈥檚 Silicon Valley, Tru-Si Technologies has developed a new
technique for thinning silicon wafers, called atmospheric downstream plasma,
which it claims could make cheaper chip stacks possible. Sergey Savastiouk,
Tru-Si鈥檚 chief executive officer, says the aim is to produce a stack of 10
interconnected chips within the next few years.
To make a connection, Tru-Si鈥檚 engineers first etch a shallow pit in the top
of the chip, and coat it with a conductor such as aluminium or copper. They then
fire a jet of oxygen and fluorine at the underside of the wafer, which dissolves
away the silicon rapidly and evenly, shaving it so thin that the conductor at
the bottom of each pit is exposed. The chips are then stacked together and
placed in a furnace. This melts the conductor and joins it to exposed contacts
on the underlying chip.
At the moment, Tru-Si can fit about 100 connections on a chip. This is no
more than can be built round the edge, but vertical connections have a big
advantage. Messages sent around the edge of a chip have to travel several
millimetres. Run them directly between layers and it鈥檚 a tiny fraction of that
distance, so layers can communicate faster with each other, speeding up the
whole processor.
But more connections would mean less time lost in bottlenecks between chips
and hence even more speed. So Michael Forshaw of the Image Processing Group at
University College London is coming at the problem from a different angle.
Sitting in a corner of the group鈥檚 seminar room is an ancient
computer鈥攊t recently celebrated its twentieth birthday, and photos of the
cake baked for the occasion are stuck to it鈥攚hich is the inspiration for
Forshaw鈥檚 work on 3D chips.
Called CLIP4A, it was an attempt to create the ultimate in image processing,
a computer that analyses images in the same way as the human brain. Rather than
dealing with an image bit by bit, the visual cortex tackles the whole thing
simultaneously. Several stages of processing are needed before we can make
conscious sense of what we鈥檙e looking at, and at each stage a different group of
neurons鈥攁 level of the visual cortex鈥攊s at work on the image.
To Forshaw, a stack of chips seemed the ideal way to copy this system in
silicon, each layer of the 3D chip acting like a different level of the cortex.
So with the help of a team of collaborators from around Europe, the CORTEX
project was formed, with the aim of creating the processors Forshaw needed at a
reasonable cost. With only a fraction of the funds available to the giant
American chip makers, Forshaw admits his project is small. But he believes they
have a solution that others have missed: liquid connections.
On the face of it, building wires out of liquid seems crazy, but what Forshaw
has in mind is no ordinary liquid. His colleague Richard Bushby of the
University of Leeds is working on a curious class of substances called discotic
liquid crystals. Their disc-shaped molecules flow like a fluid, but under the
right conditions will organise themselves into columns.
These structures have a property that has got the team excited. If electrical
charge is injected into the centres of the molecules, the columns start to act
as molecular wires. Current passes vertically through the liquid
crystal鈥攂ut is not conducted horizontally. So a thin layer of discotic
liquid crystal should provide a vast array of connections. Forshaw鈥檚 aim is
several thousand per chip.
The team is now working on a prototype stack of two to three chips. Starting
with a simple chip containing only a few transistors, they plan to thin the
silicon base of the chip, enough to allow it to connect with a layer of liquid
crystal beneath. The chip below has a set of metal pads on top to receive the
currents conducted through the liquid crystal molecular wires.
One advantage of this system, says Forshaw鈥檚 colleague Matthew Parish, is
that even with densely packed connections there is no chance of a short circuit,
as you might otherwise get when one contact melts into another.
Forshaw warns that there鈥檚 a long way to go before the CORTEX team produces a
working chip stack. Existing technologies for making holes in silicon鈥攕uch
as blasting through the wafer with a beam of ions鈥攃an鈥檛 yet produce the
densely packed holes needed to house the connecting wires. The team also has to
worry about getting power into each chip, and how to keep the stack aligned so
that the liquid crystal connects the right parts of each chip. Despite this, the
outlook is good. Forshaw is excited by developments like Tru-Si鈥檚 chip stacking
system: 鈥淭ru-Si鈥檚 announcement is a proof of concept,鈥� says Forshaw. 鈥淚t鈥檚 very
exciting for us. We will eventually combine several different technologies in
the final product.鈥� With luck, this marriage of technologies will produce fully
integrated 3D processors with many hundreds of layers.
Staying cool
The sceptics, meanwhile, want to know how these groups plan to keep their
devices from overheating. Piling chips on top of each other drastically reduces
the surface area available for cooling the electronics, so the new silicon
Manhattans might swelter in their own waste heat. Phil Marcoux of chip packing
company ChipScale has doubts, and his company has put its stacking technology on
hold, but he doesn鈥檛 think it is an insurmountable problem. 鈥淗eat dissipation
has never really been solved,鈥� says Marcoux. 鈥淲e see it on the radar screen.
It鈥檚 going to happen, but is it in one, five or thirty years? It鈥檚 a tough call
to make.鈥�
For Savastiouk, the answer may lie in the way different chips are layered. By
placing much cooler memory units between the heat-producing logic chips,
Savastiouk reckons he can stop his stack overheating. 鈥淩ight now we are
concentrating on stacking memory chips. These generate very little heat, so
dissipation isn鈥檛 a problem. Further down the line we鈥檒l combine logic and
memory chips, but we won鈥檛 stack logic chips on top of each other. The logic
chips can then be wired to a heat sink in the normal way.鈥�
Whatever the outcome, 3D chips are moving from research concept towards
marketable technology. They could soon join the list of brilliant innovations
that have kept computing power on its seemingly unstoppable upward trajectory.
Only this time the sky鈥檚 the limit.